The present invention relates to approximation techniques used in semiconductor manufacturing processes. More particularly, it relates to the prediction of unknown parameters of a wafer.
In the semiconductor manufacturing industry, there is a need to measure and predict certain wafer parameters. One such parameter is overlay error. Overlay error refers to the relative position of structures on different layers of a wafer. The greater the overlay error, the more the structures are misaligned. If the overlay error over an entire wafer is too great, the performance of an electronic device incorporating the wafer may be reduced. In a process referred to as lot dispositioning, semiconductor manufacturers determine the overlay error of a sample wafer taken from a lot of wafers. If the overlay error across the sample wafer does not meet a certain standard, the lot may be discarded.
Approximating the overlay error across an entire wafer typically involves the use of target structures. A lithography tool forms target structures at various locations on the wafer. The target structures may take many forms, such as a box in box structure. In this form, a box is created on one layer of the wafer and a second, smaller box is created on anther layer. The localized overlay error is measured by comparing the alignment between the centers of the two boxes. Such measurements are taken at locations on the wafer where target structures are available.
To properly evaluate a wafer, approximations of the overlay error at other locations may also be needed. To generate such approximations, the above measurements may be inputted into a model, such as a higher order linear model. The approximations may then be used as part of the lot dispositioning process.
The conventional models used for such approximations, however, have limitations. The models, for example, may depend on unpredictable variables, such as the optical properties of a lithography tool. The models also may have problems identifying the often complex relationships between large numbers of inputs and outputs. Therefore, in light of the deficiencies of existing approaches to the prediction of parameters for a wafer, there is a need for an approach that overcomes some of the problems of the prior art.